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in this mode compared to WS0SCBTP mode. The performance penalty in WS1SCBTP mode depends
greatly on the density and organization of conditional branch instructions in the code.
7.3.5.4 Cortex-M3 If-Then Block Folding
The Cortex-M3 offers a mechanism known as if-then block folding. This is a form of speculative
prefetching where small if-then blocks are collapsed in the prefetch buffer if the condition evaluates to
false. The instructions in the block then appear to execute in zero cycles. With this scheme, performance
is optimized at the cost of higher energy consumption as the processor fetches more instructions from
memory than it actually executes. To disable the mode, write a 1 to the DISFOLD bit in the NVIC Auxiliary
Control Register; see the Cortex-M3 Technical Reference Manual for details. Normally, it is expected
that this feature is most efficient at core frequencies above 16 MHz. Folding is enabled by default.
7.3.6 Erase and Write Operations
Both page erase and write operations require that the address is written into the MSC_ADDRB register.
For erase operations, the address may be any within the page to be erased. Load the address by
writing 1 to the LADDRIM bit in the MSC_WRITECMD register. The LADDRIM bit only has to be written
once when loading the first address. After each word is written the internal address register ADDR
will be incremented automatically by 4. The INVADDR bit of the MSC_STATUS register is set if the
loaded address is outside the flash and the LOCKED bit of the MSC_STATUS register is set if the page
addressed is locked. Any attempts to command erase of or write to the page are ignored if INVADDR
or the LOCKED bits of the MSC_STATUS register are set.
When a word is written to the MSC_WDATA register, the WDATAREADY bit of the MSC_STATUS
register is cleared. When this status bit is set, software or DMA may write the next word.
A single word write is commanded by setting the WRITEONCE bit of the MSC_WRITECMD register.
The operation is complete when the BUSY bit of the MSC_STATUS register is cleared and control of
the flash is handed back to the AHB interface, allowing application code to resume execution.
For a DMA write the software must write the first word to the MSC_WDATA register and then set the
WRITETRIG bit of the MSC_WRITECMD register. DMA triggers when the WDATAREADY bit of the
MSC_STATUS register is set.
It is possible to write words twice between each erase by keeping at 1 the bits that are not to be changed.
Let us take as an example writing two 16 bit values, 0xAAAA and 0x5555. To safely write them in the
same flash word this method can be used:
? Write 0xFFFFAAAA (word in flash becomes 0xFFFFAAAA)
? Write 0x5555FFFF (word in flash becomes 0x5555AAAA)
Note
The WRITEONCE, WRITETRIG and ERASEPAGE bits in the MSC_WRITECMD register
cannot safely be written from code in Flash. It is recommended to place a small code
section in RAM to set these bits and wait for the operation to complete. Also note that
DMA transfers to or from any other address in Flash while a write or erase operation is in
progress will produce unpredictable results.
2011-04-12 - d0001_Rev1.10
31
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